| Numéro | 52244 | Date | 25-08-2006 |
| Mobilité | PACA | Ville | ELANCOURT plan : |
| Nom | ESTEREL TECHNOLOGIES | Secteur d'activité | Indifférent |
| nb salariés | 140 | Type de contrat | CDI |
| Fonction | SoC Validation & Verification Engineer | Type de formation | indifférent |
| Expérience | 1ans | Salaire | De 31 à 38 KEuros |
| Pays | France | Langue 1 | Anglais |
| Site Internet | http://www.esterel-technologies.com | Langue 2 | Français |
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SoC Validation & Verification Engineer
Job Description
Validation and verification of a Multi-media wireless SoC based on multi-processors architecture.
Integrated in a validation team, the project consists in : Understand
design specifications and work on associated validation plans:
Develop test cases in C language, in Assembler (for ARM and DSPprocessors) or in E language (Specman environment) in order to exercise all hardware path in the design:
Sub-system, modules and peripherals integration (registers accesses, interrupts, DMA transfers)
System verification (scenario, application)
Run these tests on the RTL and debug it using software-hardware co-simulation environment, full RTL or gate environment, Specman environment.
Find and identify hardware bug and plan solutions with spec/design owners.
Profile and Experience
Minimum experience of 1 year (or more)
Skills & Competencies
Required:
Software development: C language, Assembler, Debugger
Hardware simulation and debug: RTL simulation, Modelsim
Hardware validation: Fluent or good English
Would be a great plus:
Validation tool: Specman
DSP architecture: TI DSP C54, C55
ARM architecture: ARM9, ARM11
Co-simulation: Seamless
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